AMD-V Virtualization Architecture Highlights

AMD-Virtualization (AMD-V) provides a Secure Virtual Machine (SVM) processor architecture that allows software vendors to implement secure virtualization solutions and reduce software code complexity. Here are AMD-V SVM architecture highlights commonly mentioned with reference to virtualization software:

• Host Mode - allows a hypervisor, or more generically a Virtual Machine Monitor (VMM), to execute with the highest level of privilege. This execution mode is sometimes referred to as Ring -1 mode.
• Guest Mode - allows a guest operating system to execute in privileged-mode (Ring 0) and the application stack running in user-mode (Ring 3).
• Eight SVM instructions - support virtualization, including VMRUN which enables the context switch, or world switch, from Host Mode to Guest Mode to load and execute a new guest operating system.
• Virtual Memory Control Block (VMCB) data structure - contains guest state information, including settings that define intercepts and instructions that cause transitions from Guest Mode to Host Mode.
• Address Space Identifier (ASID) - a unique identifier assignment in a Translation-Lookaside Buffer (TLB) to distinguish between co-existing host and guest entries and help to improve the performance of a context switch. A TLB is a processor cache that holds virtual-to-physical memory address mappings. Each processor core has an individual TLB.
• Simultaneous support for 16-bit, 32-bit, and 64-bit guest operating systems.
• Rapid Virtualization Indexing or Nested Paging - provides processor-powered translation of the guest memory address space to the host virtual address space, and finally to the host physical address space.

The Rapid Virtualization Indexing feature of the AMD-V SVM architecture is not leveraged in the initial release of Hyper-V.

You can obtain in-depth information on AMD-V, from the AMD64 Architecture Tech Docs at http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,00.html.