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<?xml-stylesheet type="text/xsl" href="http://vscommunity.com/utility/FeedStylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Microsoft Windows Server 2008 Hyper-V</title><link>http://vscommunity.com/groups/microsoft_windows_server_2008_hyper-v/default.aspx</link><description>Discussions of new Microsoft Windows Server 2008 Hyper-V Technology and related topics.</description><dc:language>en</dc:language><generator>CommunityServer 2008.5 SP1 (Build: 31106.3070)</generator><item><title>Intel VT Virtualization Architecture Highlights </title><link>http://vscommunity.com/groups/microsoft_windows_server_2008_hyper-v/blog/archive/2008/05/02/intel-vt-virtualization-architecture-highlights.aspx</link><pubDate>Fri, 02 May 2008 18:20:40 GMT</pubDate><guid isPermaLink="false">6c35dccf-b18d-4869-8e2f-c3244de50957:3217</guid><dc:creator>vs-admin</dc:creator><description>&lt;p&gt;Intel Virtualization Technology (Intel VT) provides a processor architecture that supports virtualization software applications through a set of extensions referred to as Virtual Machine Extensions (VMX). Here are Intel VT VMX highlights commonly mentioned with reference to virtualization software: &lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;VMX Root operating mode - allows a hypervisor or VMM to execute in fully privileged mode. &lt;/li&gt;
&lt;li&gt;VMX Non-Root operating mode - allows a guest operating system to execute in Ring 0 and the application stack in Ring 3. &lt;/li&gt;
&lt;li&gt;Ten VMX instructions - support virtualization, including VMLAUNCH which enables the context switch to load and execute a new guest operating system. &lt;/li&gt;
&lt;li&gt;Virtual Memory Control Data Structure (VMCS) - contains guest and host state information, as well as VMX control fields used to manage the transitions between VMX Root and VMX Non-Root operating modes. &lt;/li&gt;
&lt;li&gt;Virtual Processor Identifier (VPID)&amp;nbsp;- a unique identifier assignment stored in the VMCS to distinguish between co-existing host and guest entries. TLB entries are tagged with the appropriate VPID value, reducing the impact during context switches by not requiring a flush and reload of the TLB. &lt;/li&gt;
&lt;li&gt;Simultaneous support for 16-bit, 32-bit, and 64-bit guest operating systems. &lt;/li&gt;
&lt;li&gt;Extended Page Tables (EPT) - provide processor-powered translation of the guest physical memory address space to the host physical address space. &lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;Like in the case of AMD-V Rapid Virtualization Indexing, Hyper-V does not leverage the Intel VT Extended Page Tables features in the initial release. Bottom line, Intel VT and AMD-V architectures offer much similar functionality to virtualization software application developers, although their feature implementation, nomenclature, and performance may&amp;nbsp;differ from each other. &lt;/p&gt;
&lt;p&gt;Here is a reference document from Intel on this topic: &lt;a href="http://softwarecommunity.intel.com/isn/downloads/virtualization.pdf"&gt;http://softwarecommunity.intel.com/isn/downloads/virtualization.pdf&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;strong&gt;You can also&amp;nbsp;get more detailed information on the Intel VT from the Intel 64 and IA-32 Architectures Software Developer&amp;#39;s Manuals at &lt;/strong&gt;&lt;/span&gt;&lt;a href="http://www.intel.com/products/processor/manuals/"&gt;&lt;i&gt;&lt;strong&gt;http://www.intel.com/products/processor/manuals/&lt;/strong&gt;&lt;/i&gt;&lt;/a&gt;&lt;i&gt;&lt;strong&gt;.&lt;/strong&gt;&lt;/i&gt; &lt;/p&gt;</description></item><item><title>AMD-V Virtualization Architecture Highlights</title><link>http://vscommunity.com/groups/microsoft_windows_server_2008_hyper-v/blog/archive/2008/05/02/amd-v-virtualization-architecture-highlights.aspx</link><pubDate>Fri, 02 May 2008 18:19:01 GMT</pubDate><guid isPermaLink="false">6c35dccf-b18d-4869-8e2f-c3244de50957:3216</guid><dc:creator>vs-admin</dc:creator><description>&lt;p&gt;AMD-Virtualization (AMD-V) provides a Secure Virtual Machine (SVM) processor architecture that allows software vendors to implement secure virtualization solutions and reduce software code complexity. Here are AMD-V SVM architecture highlights commonly mentioned with reference to virtualization software: &lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Host Mode&amp;nbsp;- allows a hypervisor, or more generically a Virtual Machine Monitor (VMM), to execute with the highest level of privilege. This execution mode is sometimes referred to as Ring -1 mode. &lt;/li&gt;
&lt;li&gt;Guest Mode - allows a guest operating system to execute in privileged-mode (Ring 0) and the application stack running in user-mode (Ring 3). &lt;/li&gt;
&lt;li&gt;Eight SVM instructions - support virtualization, including VMRUN which enables the context switch, or world switch, from Host Mode to Guest Mode to load and execute a new guest operating system. &lt;/li&gt;
&lt;li&gt;Virtual Memory Control Block (VMCB) data structure - contains guest state information, including settings that define intercepts and instructions that cause transitions from Guest Mode to Host Mode. &lt;/li&gt;
&lt;li&gt;Address Space Identifier (ASID) - a unique identifier assignment in a Translation-Lookaside Buffer (TLB) to distinguish between co-existing host and guest entries and help to improve the performance of a context switch. A TLB is a processor cache that holds virtual-to-physical memory address mappings. Each processor core has an individual TLB. &lt;/li&gt;
&lt;li&gt;Simultaneous support for 16-bit, 32-bit, and 64-bit guest operating systems. &lt;/li&gt;
&lt;li&gt;Rapid Virtualization Indexing or Nested Paging -&amp;nbsp;provides processor-powered translation of the guest memory address space to the host virtual address space, and finally to the host physical address space. &lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;The Rapid Virtualization Indexing feature of the AMD-V SVM architecture is not leveraged in the initial release of Hyper-V.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;You can obtain in-depth information on AMD-V, from the AMD64 Architecture Tech Docs at &lt;/strong&gt;&lt;a href="http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,00.html"&gt;&lt;i&gt;&lt;strong&gt;http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,00.html&lt;/strong&gt;&lt;/i&gt;&lt;/a&gt;&lt;strong&gt;.&lt;/strong&gt; &lt;/p&gt;</description></item></channel></rss>